PCB Design & Layout

High-speed digital, mixed-signal, and RF layout for production

Professional PCB Layout Engineering

PCB layout is where good schematics become manufacturable products - or where they fail. We specialize in complex, high-speed digital designs where signal integrity, power integrity, and EMI compliance are critical. Every trace is routed with intent, every via is analyzed, and every design is optimized for manufacturing yield.

DDR4

High-Speed Digital

DDR3/4, PCIe, USB 3.x, GigE - complex routing with timing closure.

Z₀

Impedance Control

Calculated stackups, controlled routing, verified with TDR.

SI/PI

Signal & Power Integrity

Simulation-driven design for reliable high-speed performance.

DFM

Design for Manufacturing

Optimized for yield - proper clearances, testability, assembly.

High-Speed Digital Design

When edge rates are fast and wavelengths are short, transmission line effects dominate.

DDR3/DDR4 SDRAM

Challenge: Fly-by topology, strict length matching, bidirectional signals

  • Topology: Address/command fly-by, DQ point-to-point
  • Length matching: ±25ps within byte lane (DDR3), ±10ps (DDR4)
  • Impedance: 40-60Ω single-ended, group matched
  • Termination: ODT (on-die), series damping resistors
  • Vref: Reference voltage routing, low-pass filtering
  • Power: VDD, VDDQ decoupling strategy, VTT termination

USB 3.x SuperSpeed

Challenge: 5-10 Gbps differential pairs, strict loss budget

  • Impedance: 90Ω ±10% differential
  • Length matching: Intra-pair ±5 mils, pair-to-pair ±100 mils
  • Routing: Minimize vias, maintain gap spacing
  • Crosstalk: 3× trace width spacing to adjacent signals
  • Via stubs: Back-drilling for >1 GHz signals
  • Connectors: Careful breakout, GND stitching

PCIe Gen2/Gen3

Challenge: 5-8 GT/s per lane, multilane routing

  • Impedance: 85-100Ω differential
  • Lane matching: Within 5 inches across all lanes
  • Reference clock: 100 MHz CML, ±300ppm
  • AC coupling: 0.1-0.22µF series capacitors
  • Loss budget: Insertion loss <12dB @ Nyquist
  • Layer changes: Minimize, use GND vias when transitioning

Gigabit Ethernet

Challenge: 125 MHz quad differential, transformer coupling

  • Impedance: 100Ω ±10% differential
  • Intra-pair matching: ±20 mils maximum skew
  • Pair separation: Avoid crosstalk between pairs
  • Magnetics: Center tap filtering, Bob Smith termination
  • EMI: Common-mode chokes, shielding
  • ESD: TVS diodes on RJ45 pins

PCB Stackup Design - Rick Hartley Methodology

Solid ground planes, power distributed on signal layers. NO split planes.

4-Layer Stackup (Preferred)

Two solid ground planes, power distributed on signal layers.

Layer 1 (Top): Signal + Power Distribution - High-speed signals, copper pours for power rails

Layer 2: Ground Plane - Solid copper, NO SPLITS

Layer 3: Ground Plane - Solid copper, NO SPLITS

Layer 4 (Bottom): Signal + Power Distribution - Secondary signals, additional power routing

Typical Trace Widths (1oz copper, FR-4)

  • 50Ω microstrip (L1): ~10-12 mils (4 mil height)
  • 100Ω differential (L1): 6 mil trace, 6 mil gap
  • Power traces: Width based on current (1A ≈ 10-15 mils)

Key Advantages

  • ✓ Return paths: Two solid ground planes provide excellent return current paths
  • ✓ NO split planes: Eliminates return path discontinuities
  • ✓ Signal integrity: Clean references for all high-speed signals
  • ✓ Multi-voltage: Distribute all voltages on signal layers via pours and traces

6-Layer Stackup (High-Performance)

Multiple ground planes, optimal for high-speed designs.

Layer 1: Signal + Power - High-speed digital, power distribution

Layer 2: Ground Plane - Solid, reference for L1

Layer 3: Signal - Stripline, orthogonal routing

Layer 4: Signal - Stripline, orthogonal to L3

Layer 5: Ground Plane - Solid, reference for L3/L4/L6

Layer 6: Signal + Power - Secondary signals, power distribution

Advantages

  • Shielding: Signals sandwiched between planes
  • Return paths: Clean, unbroken ground references
  • NO split planes: All ground planes kept solid
  • Power distribution: Multiple voltages distributed on signal layers

When to Use

  • DDR3/DDR4 memory interfaces
  • High-speed serial (USB 3.x, PCIe, 10GbE)
  • Dense BGAs with complex fanout
  • EMI-sensitive applications

Impedance Calculation

Designing for controlled impedance requires accurate calculations.

Microstrip (Surface Layer)

Formula (approximate):

Z₀ ≈ 87 / √(εᵣ + 1.41) × ln(5.98h / (0.8w + t))

  • w: Trace width
  • h: Height above plane
  • t: Copper thickness
  • εᵣ: Dielectric constant (FR-4 ≈ 4.2-4.5)

Stripline (Internal Layer)

Embedded between planes:

Z₀ ≈ 60 / √εᵣ × ln(4h / (0.67πw))

  • More consistent impedance (no soldermask)
  • Better EMI shielding
  • Preferred for critical high-speed signals

Differential Pairs

Zdiff = 2 × Z₀ × (1 - 0.48e^(-0.96s/h))

  • s: Gap between traces
  • h: Height to reference plane
  • Coupling increases with smaller gap
  • Typical edge-coupled: s/w ≈ 1:1 for tight coupling

Via Design & Transitions

Vias are discontinuities - design them carefully.

Via Stub Resonance

Problem: Unused via length acts as stub, resonates at:

f = c / (4 × stub_length × √εᵣ)

  • For FR-4 (εᵣ=4.3), 100 mil stub resonates at ~5.6 GHz
  • Solution: Back-drilling to remove unused barrel
  • Alternative: Blind/buried vias (more expensive)
  • Best: Route on single layer when possible

Via Return Path

Critical: GND vias adjacent to signal vias

  • Place GND via within 20-30 mils of signal via
  • Return current must have low-impedance path
  • Failing to do this increases ground bounce
  • Especially critical for layer transitions

Differential Via Transitions

  • Both signals transition together (minimize skew)
  • Vias same length, symmetrically placed
  • GND vias on both sides of differential pair
  • Maintain differential impedance through transition

Power Integrity (PI)

Clean power distribution is as critical as signal routing.

Decoupling Strategy

Multi-tiered approach for broad frequency coverage:

  • Bulk (100µF): Low-frequency, power supply transients
  • Ceramic (10µF): Mid-frequency load steps
  • Bypass (0.1µF): High-frequency switching noise
  • Ultra-HF (0.01µF): GHz-range harmonics
  • Placement: As close to power pins as possible
  • Vias: Multiple vias to power/GND planes (low inductance)

Plane Capacitance

Power and ground planes form distributed capacitance:

C = (ε₀ × εᵣ × A) / d

  • Closer planes = more capacitance
  • Typical 4-layer: ~50-100 pF/sq-inch
  • Helps with high-frequency decoupling
  • Minimize distance between VDD and GND planes
  • Beware of plane resonances (anti-resonance)

Power Distribution Strategy

DO NOT USE SPLIT PLANES - Use power pours on signal layers instead:

  • Ground planes: ALWAYS keep solid - NO SPLITS EVER
  • Power planes: Avoid dedicated power planes that require splitting
  • Power distribution: Use copper pours and wide traces on signal layers (L1, L4, L6)
  • Multi-voltage: Each voltage gets its own copper pour on signal layers
  • Return paths: Split planes create gaps in return current paths - eliminate this problem entirely
  • Rick Hartley principle: Solid ground planes are sacred - never compromise signal integrity with splits
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Why This Matters

  • Split planes force return currents to take long paths around gaps
  • Return path discontinuities cause EMI and signal integrity problems
  • Solid ground planes provide consistent impedance references
  • Power on signal layers gives flexibility without compromising signal integrity

Power Distribution Network (PDN)

Target impedance method:

Ztarget = Vripple / Imax

  • Example: 50mV ripple, 5A load → 10mΩ target
  • Achieve with parallel capacitors + low-ESR design
  • Plane inductance dominates at high frequency
  • Via inductance ~1nH each (minimize with multiple vias)
  • Use PDN simulation tools (HyperLynx, ADS, CST)

Design for Manufacturing (DFM)

Fabrication Guidelines

  • Minimum trace: 5 mils (4 mils for fine-pitch)
  • Minimum space: 5 mils (4 mils for high-density)
  • Minimum drill: 8 mils (6 mils for microvias)
  • Annular ring: 4 mils minimum (helps yield)
  • Soldermask: 3 mils clearance around pads
  • Silkscreen: 5 mils line width, 30 mils text height

Assembly Considerations

  • Component spacing: 40-50 mils minimum
  • Edge clearance: 100+ mils from board edge
  • Fiducials: 3 minimum, opposing corners + center
  • Tooling holes: For panel assembly
  • Polarization marks: Pin 1, polarity indicators
  • Test points: 50 mil diameter, accessible

Thermal Management

  • Thermal reliefs: On power plane connections (unless high current)
  • Thermal vias: Under QFNs, thermal pads (9-16 vias)
  • Copper pour: Heat spreading, GND stitching
  • Via arrays: For heat transfer to back side
  • Keep-out zones: Under hot components

Testability (DFT)

  • Test points: Power rails, critical signals
  • JTAG access: Header or test points
  • LED indicators: Power, activity, status
  • Jumpers: Configuration options
  • Bed-of-nails: Test pad patterns for ICT

CAD Tools & Workflow

1

Schematic

Altium Designer, multi-sheet hierarchical design with DRC

1-3 weeks
2

Stackup

Layer assignment, impedance calculations, material selection

1-2 days
3

Placement

Component placement optimized for routing, thermal, manufacturing

2-5 days
4

Routing

High-speed first, length matching, impedance control, DRC clean

1-3 weeks
5

Verification

DRC, LVS, SI simulation, fab file review, peer review

3-5 days

Typical PCB design timeline: 4-8 weeks depending on complexity, component density, and layer count. Rush service available for simple designs.

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